Chip capacitor embedment method

ABSTRACT

A method of embedding a chip capacitor in a printed circuit board including a first conductive layer and a dielectric layer placed on the first conductive layer includes removing the dielectric layer to form a cavity exposing the first conductive layer; seating a chip capacitor in the cavity; filling a filled material at a space excluding a space occupied by the chip capacitor in the cavity; forming a via penetrating the filled material and being connected to the chip capacitor; and stacking a conductive material to constitute a second conductive layer in surfaces of the via and the dielectric layer and in an surface of the filled material filled in the cavity.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a U.S. divisional application filed under 37 CFR1.53(b) claiming priority benefit of U.S. patent application Ser. No.12/007,793, filed Jan. 15, 2008, which claims earlier priority benefitto Korean Patent Application No. 10-2007-0097722, filed with the KoreanIntellectual Property Office on Sep. 28, 2007, the disclosures of whichare incorporated herein by reference.

BACKGROUND

1. Field

The present invention relates to a printed circuit board, morespecifically to a printed circuit board having an embedded chipcapacitor and a chip capacitor embedding method that can use a seriesconnection structure between a chip capacitor and a via as anelectromagnetic bandgap structure.

2. Description of the Related Art

Various apparatuses such as mobile communication terminals, personaldigital assistants (PDA), laptop computers and digital multimediabroadcasting (DMB) devices have been launched in order to meet today'strend that, mobility is considered as one of the most important issues.

Such apparatuses include a printed circuit board, which is configured tocompound analog circuits (e.g. radio frequency (RF) circuits) anddigital circuits for wireless communication.

FIG. 1 is a sectional view showing a printed circuit board including ananalog circuit and a digital circuit. Although a 4-stacked in printedcircuit board is illustrated, various printed circuit boards such as 2and 6-stacked in printed circuit boards can be applied. Here, the analogcircuit is assumed to be an RF circuit.

The printed circuit board 100 includes metal layers 110-1, 110-2, 110-3and 110-4 (hereinafter, collectively referred to as 110), dielectriclayers 120-1, 120-2 and 120-3 (hereinafter, collectively referred to as120) stacked in between the metal layers 110, a digital circuit 130mounted on the top metal layer 110-1 and an RF circuit 140.

If it is assumed that the metal layer 110-2 is a ground layer and themetal layer 110-3 is a power layer, a current passes through a via 160connected between the ground layer 110-2 and the power layer 110-3 andthe printed circuit board 100 performs a predetermined operation orfunction.

Here, an operation frequency of the digital circuit 130 and anelectromagnetic (EM) wave 150 by harmonics components are transferred tothe RF circuit 140, to thereby generate a problem mixed signals. Themixed signal problem is generated due to the EM wave, having a frequencywithin the frequency band in which the RF circuit 140 is operated, inthe digital circuit 130. This problem results in obstructing theaccurate operation of the RF circuit 140. For example, when the RFcircuit 140 receives a signal having a certain frequency band,transferring the EM wave 150 including the signals having the certainfrequency band from the digital circuit 130 may make it difficult toaccurately receive the signal having the certain frequency band.

Solving the problem mixed signals becomes more difficult due to thehigher operation frequency of the digital circuit 130 according to theincreased complexity of electronic apparatuses.

The decoupling capacitor method, which is a typical solution for powernoise, is not adequate for high frequencies. Accordingly, it isnecessary to intercept or decrease the noise of the high frequenciesbetween the RF circuit 140 and the digital circuit 130.

FIG. 2 is a sectional view showing an electromagnetic bandgap structurethat solves a problem mixed signals between an analog circuit and adigital circuit in accordance with a conventional art, and FIG. 3 is aplan view showing a metal plate configuration of the electromagneticbandgap structure shown in FIG. 2. FIG. 4 is a perspective view showingthe electromagnetic bandgap structure shown in FIG. 2, and FIG. 5 is aschematic view showing an equivalent circuit of the electromagneticbandgap structure shown in FIG. 2.

The electromagnetic bandgap structure 200 includes a first metal layer210-1, a second metal layer 210-2, a first dielectric layer 220 a asecond dielectric layer 220 b, a meal plate 232 and a via 234.

The first metal layer 210-1 and the metal plate 232 are connected toeach other through the via 234. A mushroom type structure 230 is formedto include the metal plate 232 and the via 234 (refer to FIG. 4).

If the first metal layer 210-1 is a ground layer, the second metal layer210-2 is a power layer. Also, if the first metal 210-1 is the powerlayer, the second layer 210-2 is the ground layer.

In other words, the repeated formation of the mushroom type structure230 (refer to FIG. 3) results in a bandgap structure preventing a signalhaving a certain frequency band from being penetrated. At this time, themushroom type structures 230, including the metal plates 232 and thevias 234, are repeatedly formed between the ground layer and the powerlayer.

The function preventing a signal having a certain frequency band frombeing penetrated, which is based on resistance R_(E) and R_(P),inductance L_(E) and L_(P), capacitance C_(E), C_(P) and C_(G) andconductance G_(P) and G_(E), is approximated to the equivalent circuitshown in FIG. 5.

A mobile communication terminal is a good example for an electronicapparatus employing the board in which the digital circuit and the RFcircuit are realized together. In the case of the mobile communicationterminal, solving the problem mixed signals needs the noise shielding ofan operation frequency band of the RF circuit between 0.8 and 2.0 GHz.The small sized mushroom type structure is also required. However, theforegoing electromagnetic bandgap structure may not satisfy the twoconditions needed to solve the mixed signal problem simultaneously. Inother words, the smaller sized mushroom type structure causes thebandgap frequency band shielding the noise to be increased. Also, thelarger sized mushroom type structure needs the increase of the size,thickness and volume of the printed circuit board.

In accordance with the conventional art, the mushroom type structuresare required to be repeatedly arranged close to each other in order tobe used as the electromagnetic bandgap structure. However, this may havea bad influence on signal integrity. Here, the signal integrityindicates the accuracy of signal transfer such as whether to delaytransferring a signal and whether to maintain a signal type as aperformance evaluation index related to how stable a signal istransferred in time.

Also, in the case of having the complex line structure in which thedigital circuit and the RF circuit are realized on the same board likethe main board of a mobile phone or mounting a lot of active elementsand passive elements in the same small-sized board as a system inpackage (SiP) board, a lot of design limitations are required to berecovered to realize the electromagnetic bandgap structure by theconventional mushroom type structure.

SUMMARY

Accordingly, the present invention provides a printed circuit boardhaving an embedded chip capacitor that uses the series connectionstructure between the chip capacitor and a via as an electromagneticbandgap structure to solve a problem mixed signals, various electricalparts and elements including an analog circuit and a digital circuitbeing mounted in the printed circuit board.

The present invention also provides a printed circuit board having anembedded chip capacitor that can simply prevent the noise having adesired frequency band by using the cavity capacitor having a simplestructure as an electromagnetic bandgap structure.

In addition, the present invention provides a compact, thin film andlight-weighted printed circuit board having an embedded chip capacitorwith high capacity and high efficiency through a simple fabricationprocess and a reduced fabrication time and cost.

An aspect of the present invention features a printed circuit boardhaving an embedded chip capacitor including a first conductive layer; asecond conductive layer, placed away from the first conductive layer; achip capacitor, placed between the first conductive layer and the secondconductive layer and having a second electrode, connected to the secondconductive layer; and a via, connecting the first conductive layer to afirst electrode of the chip capacitor.

Here, a via land can be formed in one end part of the via, and the viacan be connected to the first electrode through the via land formed inthe one end part of the via, and the other end part of the via can beconnected to the first conductive layer.

The chip capacitor can include a first electrode, a dielectric member,placed on the first electrode, and a second electrode, placed on thedielectric member. At this time, the chip capacitor can be seated on thevia land.

The chip capacitor can include a dielectric member, a first electrode,which is coupled to a right side of the dielectric member, and a secondelectrode, which is coupled to a left side of the dielectric member. Atthis time, a clearance hole can be formed in a part corresponding to aposition of the first electrode in the second conductive layer to allowthe first electrode to be electrically disconnected to the secondconductive layer.

Another aspect of the present invention features a printed circuit boardhaving an embedded chip capacitor including a first conductive layer; asecond conductive layer, placed away from the first conductive layer; achip capacitor, having a first electrode connected to the firstconductive layer through being seated in a cavity formed between thefirst conductive layer and the second conductive layer; a filledmaterial, filled in a space excluding the space occupied by the chipcapacitor in the cavity; and a via, penetrating the filled material andconnecting the second conductive layer to the second electrode of thechip capacitor.

Here, any one of the first conductive layer and the second conductivelayer can be a power layer, and the other end part can be a ground part.

An etched pattern can be formed in an open-curved line shape in asurrounding area of a part corresponding to a position of the via or thechip capacitor in the first conductive layer or the second conductivelayer.

The etched pattern can have a spiral shape.

The chip capacitor can be coupled to an inductance component by the via,connected to the chip capacitor in series, to intercept the transfer ofan electromagnetic wave having a desired frequency band.

A plurality of series connection structures between the chip capacitorand the via can be arranged in a noise transferable path between a noisesource and a noise prevented destination.

The printed circuit board can be mounted with a digital circuit and ananalog circuit, and the noise source and the noise prevented destinationcan correspond to one and the other, respectively, of positions in whichthe digital circuit and the analog circuit are supposed to be mounted inthe printed circuit board.

The series connection structure between the chip capacitor and the viacan be arranged in a band structure in the noise transferable path.

The band structure can have a shape enveloping at least one of the noisesource and the noise prevented destination. For example, the bandstructure can have any one of closed loop, rectangular shape with oneside open, and ‘L’ shapes.

The band structure can have a straight-line shape of at least one lineto separate the noise source and the noise prevented destination bycrossing the area between the noise source and the noise preventeddestination.

Another aspect of the present invention features a method of embedding achip capacitor in a printed circuit board including a first conductivelayer and a dielectric layer placed on the first conductive layer, themethod including removing the dielectric layer to form a cavity exposingthe first conductive layer; seating a chip capacitor in the cavity;filling a filled material at a space excluding the space occupied by thechip capacitor in the cavity; forming a via penetrating the filledmaterial and being connected to the chip capacitor; and stacking aconductive material to constitute a second conductive layer in surfacesof the via and the dielectric layer and in an surface of the filledmaterial filled in the cavity.

Here, chip capacitor can include a first electrode, a dielectric member,placed on the first electrode, and a second electrode, placed on thedielectric member, and the first electrode is connected to the firstconductive layer, and the second electrode can be connected to thesecond conductive layer through the via.

The present invention can further include forming an etched pattern inan open-curved line shape in a surrounding area of a part correspondingto a position in which the cavity is supposed to be formed in the firstconductive layer.

The present invention can further include forming an etched pattern inan open-curved line shape in a surrounding area of a part correspondingto a position in which the via is formed in the second conductive layer

Here, etched pattern can have a spiral shape.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the presentinvention will become better understood with regard to the followingdescription, appended claims and accompanying drawings where:

FIG. 1 is a sectional view showing a printed circuit board includinganalog circuit and a digital circuit;

FIG. 2 is a sectional view showing an electromagnetic bandgap structurethat solves a problem mixed signals between an analog circuit and adigital circuit in accordance with a conventional art;

FIG. 3 is a plan view showing a metal plate configuration of theelectromagnetic bandgap structure shown in FIG. 2;

FIG. 4 is a perspective view showing the electromagnetic bandgapstructure shown in FIG. 2;

FIG. 5 is a schematic view showing an equivalent circuit of theelectromagnetic bandgap structure shown in FIG. 2;

FIG. 6 is a side view showing a printed circuit board having an embeddedchip capacitor in accordance with a first embodiment of the presentinvention;

FIG. 7 is a schematic view showing an equivalent circuit of the printedcircuit board shown in FIG. 6;

FIG. 8A is a side view showing a printed circuit board having anembedded chip capacitor in accordance with a second embodiment of thepresent invention;

FIG. 8B illustrates the type of an etched pattern when the printedcircuit board shown in FIG. 8A is viewed from an upper side;

FIG. 8C is a schematic view showing an equivalent circuit of the printedcircuit board shown in FIG. 8A;

FIG. 9A is a side view showing a printed circuit board having anembedded chip capacitor in accordance with a third embodiment of thepresent invention;

FIG. 9B illustrates the type of an etched pattern when the printedcircuit board shown in FIG. 9A is viewed from a lower side;

FIG. 9C is a schematic view showing an equivalent circuit of the printedcircuit board shown in FIG. 9A;

FIG. 10A is a side view showing a printed circuit board having anembedded chip capacitor in accordance with a fourth embodiment of thepresent invention;

FIG. 10B illustrates a clearance hole when the printed circuit boardshown in FIG. 10A is viewed from an upper side;

FIG. 11A through FIG. 11C are examples illustrating a printed circuitboard in which a chip capacitor is arranged in a band structure inaccordance with the present invention;

FIG. 12A is a side view showing a printed circuit board having anembedded chip capacitor in accordance with a fifth embodiment of thepresent invention;

FIG. 12B is a side view showing a printed circuit board having anembedded chip capacitor in accordance with a sixth embodiment of thepresent invention;

FIG. 12C is a side view showing a printed circuit board having anembedded chip capacitor in accordance with a seventh embodiment of thepresent invention;

FIG. 13A through 13F illustrate the method for embedding a chipcapacitor in the case of the printed circuit board shown in FIG. 12A;

FIG. 12A illustrates a simulation model for checking whether the seriesconnection structure between a via and a chip capacitor embedded in aprinted circuit board can be used as an electromagnetic bandgap inaccordance with the present invention; and

FIG. 14B shows a computer-simulation result when the simulation modelshown in FIG. 14A is applied.

DESCRIPTION OF EMBODIMENTS

Since there can be a variety of permutations and embodiments of thepresent invention, certain embodiments will be illustrated and describedwith reference to the accompanying drawings. This, however, is by nomeans to restrict the present invention to certain embodiments, andshall be construed as including all permutations, equivalents andsubstitutes covered by the spirit and scope of the present invention.Throughout the drawings, similar elements are given similar referencenumerals. Throughout the description of the present invention, whendescribing a certain technology is determined to evade the point of thepresent invention, the pertinent detailed description will be omitted.

Terms such as “first” and “second” can be used in describing variouselements, but the above elements shall not be restricted to the aboveterms. The above terms are used only to distinguish one element from theother. For instance, the first element can be named the second element,and vice versa, without departing the scope of claims of the presentinvention. The term “and/or” shall include the combination of aplurality of listed items or any of the plurality of listed items

When one element is described as being “connected” or “accessed” toanother element, it shall be construed as being connected or accessed tothe other element directly but also as possibly having another elementin between. On the other hand, if one element is described as being“directly connected” or “directly accessed” to another element, it shallbe construed that there is no other element in between.

The terms used in the description are intended to describe certainembodiments only, and shall by no means restrict the present invention.Unless clearly used otherwise, expressions in the singular numberinclude a plural meaning. In the present description, an expression suchas “comprising” or “consisting of” is intended to designate acharacteristic, a number, a step, an operation, an element, a part orcombinations thereof, and shall not be construed to preclude anypresence or possibility of one or more other characteristics, numbers,steps, operations, elements, parts or combinations thereof.

Unless otherwise defined, all terms, including technical terms andscientific terms, used herein have the same meaning as how they aregenerally understood by those of ordinary skill in the art to which theinvention pertains. Any term that is defined in a general dictionaryshall be construed to have the same meaning in the context of therelevant art, and, unless otherwise defined explicitly, shall not beinterpreted to have an idealistic or excessively formalistic meaning.

Hereinafter, some embodiments of the present invention will be describedin detail with reference to the accompanying drawings. The overlappingdescription that is identically applicable to each embodiment will beomitted.

FIG. 6 is a side view showing a printed circuit board having an embeddedchip capacitor in accordance with a first embodiment of the presentinvention, and FIG. 7 is a schematic view showing an equivalent circuitof the printed circuit board shown in FIG. 6.

Referring to FIG. 6, a printed circuit board having an embedded chipcapacitor in accordance with a first embodiment of the present inventioncan include a first conductive layer 310, a second conductive layer 320,a dielectric layer 330, a chip capacitor 340 and a via 350.

Any one of the first conductive 310 and the second conductive layer 320can be used as a power layer, and the other can be used as a groundlayer. Accordingly, the first conductive 310 and the second conductivelayer 320 can be away from each other through the dielectric layer 330placed therebetween in order to allow the first conductive 310 and to beelectrically disconnected to the second conductive layer 320.

The chip capacitor 340 can be embedded between the first conductivelayer 310 and the second conductive layer 320 in the printed circuitboard. The chip capacitor 340 can include a first electrode 341, adielectric member 343 placed on the first electrode 341 and a secondelectrode 342 placed on the dielectric member 343. At this time, thesecond electrode 342 can be electrically connected to the secondconductive layer 320 through a surface contact method, and the firstelectrode 341 can be electrically connected to the first conductivelayer 310 through the via 350. For this, a via land 350 a can be formedin one end part of the via 350. The via 350 can be connected to thefirst electrode 341 through the via land 350 a formed in the one endpart, and the other end part of the via 350 can be connected to thefirst conductive layer 310. In other words, the via land 350 a, which isfor recovering a position error, can be formed larger than the sectionalarea of the via 350. The chip capacitor 340 can be seated on the vialand 350 a.

FIG. 7 is a schematic view showing an equivalent circuit of the printedcircuit board shown in FIG. 6. As shown in the schematic view of FIG. 7,in accordance with the present invention, the chip capacitor 340 and thevia 350 formed between the first conductive layer 310 and the secondconductive layer 320 can function as a capacitance component and aninductance component, respectively. The chip capacitor 340 and the via350 can be connected to each other in series. As such, the presentinvention can function as a band reject filter by using the LC seriesconnection structure between the chip capacitor 340 and the via 350, tothereby intercept the transfer of an electromagnetic wave having afrequency band. In other words, since the present invention functions asthe band reject filter through the LC series connection by the chipcapacitor 340 and the via 350, which is the ‘structural property’ of theprinted circuit board, the series connection structure between the chipcapacitor 340 and the via 350 can be used as the electromagneticstructure.

Accordingly, if the diameter, length and shape of the via 350 areprecisely designed and controlled in the present invention, the via 350can be manufactured to have a desired inductance value. Also, if thechip capacitor 340 having a desired capacitance value is selectedconsidering the thickness and area size of the dielectric member 343 ofthe chip capacitor 340 and the type and dielectric constant of thedielectric material forming the dielectric member 343 and the selectedchip capacitor 340 is applied to the printed circuit board, the presentinvention can intercept the transfer of an electromagnetic wave having adesired frequency band. This can solve the mixed signal and noiseproblem of the printed circuit board.

In particular, since it is possible to acquire a high-capacity andhigh-efficiency capacitance value in accordance with the presentinvention, the smaller-sized electromagnetic bandgap structure can berealized in a small space as compared with the conventional mushroomtype structure. The preventing efficiency can be also improved.

FIG. 8A is a side view showing a printed circuit board having anembedded chip capacitor in accordance with a second embodiment of thepresent invention, FIG. 8B illustrates the type of an etched patternwhen the printed circuit board shown in FIG. 8A is viewed from an upperside and FIG. 8C is a schematic view showing an equivalent circuit ofthe printed circuit board shown in FIG. 8A. FIG. 9A is a side viewshowing a printed circuit board having an embedded chip capacitor inaccordance with a third embodiment of the present invention, FIG. 9Billustrates the type of an etched pattern when the printed circuit boardshown in FIG. 9A is viewed from a lower side and FIG. 9C is a schematicview showing an equivalent circuit of the printed circuit board shown inFIG. 9A.

Referring to FIG. 8A, in the case of a printed circuit board having anembedded chip capacitor in accordance with a second embodiment of thepresent invention, it can be recognized that a surrounding area of apart corresponding to the position of the chip capacitor 340 in thesecond conductive layer 320 is partially being etched to have a patternin the printed circuit board in accordance with the first embodiment ofFIG. 6, which was described above. Referring to FIG. 9A, in the case ofa printed circuit board having an embedded chip capacitor in accordancewith a third embodiment of the present invention, it can be alsorecognized that an etched pattern 370 is being formed in a surroundingarea of a part corresponding to the position of the via 350 in the firstconductive layer 310 in the printed circuit board in accordance with thefirst embodiment of FIG. 6.

Here, the etched pattern 370 can be formed in a spiral type as shown inFIG. 8 b and FIG. 9B. As such, the etched pattern 370 formed in thespiral type can have some benefits as follows. The spiral type is thepattern type which can be manufactured to have the maximum patternlength in a narrow area. At this time, the etched pattern 370 formed inthe first conductive layer 310 or the second conductive layer 320 canfunction as the inductance component in the printed circuit board.

Accordingly, the spiral type as the etched pattern 370 can realize theinductance having the largest value in the narrow area or surface. Inaddition, the spiral type, which includes the self inductance, formed ina lengthwise direction, and the mutual inductance, formed byintersection between spiral type etched patterns (e.g. 370-1 and 370-3or 370-2 and 370-4 in FIG. 9A and FIG. 9B in FIG. 8A), can easilyrealize a larger inductance value.

Accordingly, the printed circuit board in accordance with the second orthird embodiment of the presented invention can more efficiently anduniversally use the function as the electromagnetic bandgap structureintercepting the transfer of an electromagnetic wave having a desiredfrequency band by the etched pattern 370, which is additionallyconnected to the chip capacitor 340 in series, together with theinductance component by the via 350 (refer to FIG. 8C and FIG. 9C). Thisis because adjusting the inductance value according to the designmodification of the diameter, length and shape of the via 350 betweenany two conductive layers of the printed circuit board having thedetermined size, thickness and area size can not but be partiallyrestricted.

As compared with this, to obtain a desired inductance value by designingand controlling the shape, length, width and area size of the etchedpattern 370 can be more easily performed on the design. This canincrease the usability as the electromagnetic bandgap structure of thepresent invention.

Although FIG. 8A through FIG. 9C illustrate the etched pattern 370 ofthe spiral type, the etched pattern 370 can be designed and manufacturedin various types (e.g. a trace type and a bar type). However, the etchedpattern 370 can have an open-curved shape. This is because if the etchedpattern 370 has a closed-curved shape, the electrical connection betweenthe first conductive layer 310 and the first electrode 341 of the chipcapacitor 340 or between the second conductive layer 320 and the secondelectrode 342 is broken, which results in allowing the chip capacitor340 to be unable to function as the capacitor. Accordingly, any etchedpattern 370 having an open-curved shape capable of electricallyconnecting the chip capacitor 340 to each conductive layer can beapplied to the present invention without restriction.

FIG. 10A is a side view showing a printed circuit board having anembedded chip capacitor in accordance with a fourth embodiment of thepresent invention, and FIG. 10B illustrates a clearance hole when theprinted circuit board shown in FIG. 10A is viewed from an upper side.

Referring to FIG. 10A and FIG. 10B, a printed circuit board having anembedded chip capacitor in accordance with a fourth embodiment of thepresent invention can have the shape in which a clearance hole 360 isformed in a part of the second conductive layer 320.

The reason that the clearance hole 360 is formed at the secondconductive layer 320 in the printed circuit board in accordance with thefourth embodiment of the present invention is as follows. All chipcapacitors embedded in the printed circuit board in accordance with theforgoing embodiments are the flake type. The flake type indicates thatthe electrodes are formed in an upper side and a lower side,respectively, and the dielectric member is placed between theelectrodes. In the chip capacitor of the flake type, since the twoelectrodes are in no surface-contact with each other on the sameconductive layer because the two electrodes are arranged in the upperside and the lower side, respectively, as shown in FIG. 10A, it isunnecessary that the clearance hole 360 is formed in any conductivelayer.

However, the fourth embodiment of the present invention uses a chipcapacitor of an end-banded type. The end-banded type indicates that theelectrodes are formed in a lower side and a right side, respectively,and the dielectric member is placed between the electrodes. In the chipcapacitor of the end-banded type, since the two electrodes may be insurface-contact with each other on the same conductive layer because thetwo electrodes are arranged in the left side and the right side,respectively, of a plane. Accordingly, in the case of FIG. 10A, theclearance hole 360 can be formed in a part of corresponding to theposition of the first electrode 341 in the second conductive layer 320,in order to allow the first electrode 341 and the second electrode 342of the chip capacitor 340 to be electrically disconnected to the secondconductive layer 320.

Of course, the printed circuit board in accordance with the foresaidfourth embodiment of the present invention can function as theelectromagnetic bandgap structure by the same principle (i.e. the seriesconnection structure between the chip capacitor 340 and the via 350) asdescribed with reference to FIG. 6.

FIG. 11A through FIG. 11C are examples illustrating a printed circuitboard in which a chip capacitor is arranged in a band structure inaccordance with the present invention. Based on the view from an upperside of the printed circuit board, each part corresponding to theposition embedded with the series connection structure between the chipcapacitor 340 and the via 350 is represented as circles (actually, whenviewed from an upper side, the chip capacitor 340 only is illustrated)for the convenience of illustration.

In FIG. 11A through FIG. 11C, a region A 410 and a region B indicatestwo regions necessary to prevent mutual interference, respectively, dueto using different frequency bands. The below description assumes thatthe region A 410 is mounted with the RF circuit and the region B 420 ismounted with the digital circuit in the case of a mobile phone mainboard 400. In other words, if any one of the region A 410 and the regionB 420 functions as a noise source in their mutual relationship, theother is determined as a noise prevented destination.

Through FIG. 11A through FIG. 11C, it can be recognized that a pluralityof series connection structures between the chip capacitor 340 and thevia 350 (or between the chip capacitor 340, the via 350 and the etchedpattern 370) are arranged in a path between the noise source and thenoise prevented destination, placed in the printed circuit board. Inother words, the present invention can use the method having andembedding the plurality of series connection structures between the chipcapacitor 340 and the via 350 on the pertinent noise-transferable pathin order to prevent a mixed signal or noise having a frequency band,which is possible to be generated from an electrical element placed atthe noise source and to have an affect on the other electrical elementplaced at the noise prevented destination.

In particular, FIG. 11A shows a band structure in which the plurality ofseries connection structures between the chip capacitor 340 and the via350 are arranged to envelop the four sides of a region A 410 and aregion B 420, respectively, in a closed loop shape. Of course, unlikeFIG. 11A, it is possible to envelop either the noise source or the noiseprevented destination.

FIG. 11B shows the plurality of series connection structures between thechip capacitor 340 and the via 350 envelops the two or three sides ofthe region A 410 and the region B 420, respectively, in a rectangularshape with one side open or an ‘L’ shape instead of enveloping the foursides as shown in FIG. 11A. As such, it is possible to envelop eachregion in the shape of the board with one side open. Accordingly, it isobvious that the band structure can have the shape having the rotationaldisplacement of the rectangular shape with one side open or an ‘L’ shapeaccording to the shape of the board and the position of the closedregion.

Unlike FIG. 11A and FIG. 11B, the FIG. C shows that the plurality ofseries connection structures between the chip capacitor 340 and the via350 are arranged in straight-line shapes having at least one line toseparate the region A 410 and the region B 420 by crossing the areabetween the two regions, instead of enveloping each prevented region.

In addition to FIG. 11A through FIG. 11C, it is understandable to anyperson of ordinary skill in the art that the cavity capacitors can bearranged in the noise-transferable path between the noise source and thenoise prevented destination in various ways.

For example, it is unnecessary that the size, shape, area size andlength, respectively, of the plurality of series connection structuresbetween the chip capacitor 340 and the via 350 are the same. At leastone of the size, shape, area size and length of the plurality of seriesconnection structures between the chip capacitor 340 and the via 350 canbe differently can be determined. Since these factors are closelyrelated to a frequency band desired to be prevented, the factors can beoptimally selected according to the prevented desired frequency band orthe design specifications.

In other words, if it is necessary to more broadly set the frequencyband of the noise desired to be prevented, it can be preferable toalternately or repeatedly arrange the plurality of series connectionstructures between the chip capacitor 340 and the via 350 having varioussize, shape, area size and length according to the necessary frequencyband. Reversely, if it is necessary to more narrowly set and moreaccurately prevent the frequency band of the noise desired to beprevented, it can be preferable to arrange series connection structuresbetween the chip capacitor 340 and the via 350 having the same size andshape at shorter intervals or repeatedly in a plurality of linesaccording to the necessary frequency band.

FIG. 12A is a side view showing a printed circuit board having anembedded chip capacitor in accordance with a fifth embodiment of thepresent invention, FIG. 12B is a side view showing a printed circuitboard having an embedded chip capacitor in accordance with a sixthembodiment of the present invention and FIG. 12C is a side view showinga printed circuit board having an embedded chip capacitor in accordancewith a seventh embodiment of the present invention.

Referring to FIG. 12A, in a printed circuit board having an embeddedchip capacitor in accordance with a fifth embodiment of the presentinvention, the chip capacitor 340 can be seated in a cavity (refer to380 a of FIG. 13C to be described below) which is formed by removing apart of the dielectric layer 330 placed between the first conductivelayer 310 and the second conductive layer 320. Seating the chipcapacitor 340 in the cavity allows the first electrode 341 to beconnected to the first conductive layer 310. At this time, a filledmaterial 380 can be filled in a space excluding the space occupied bythe chip capacitor 340 in the cavity formed between the first conductivelayer 310 and the second conductive layer 320, and the via 350 canpenetrate the filled material 380 to electrically connect the secondelectrode 342 of the chip capacitor 340 to the second conductive layer320.

Referring to FIG. 12B and FIG. 12C, in the case of a sixth embodimentand a seventh embodiment of the present invention, it can be recognizedthat the similar etched pattern to that of FIG. 8A and FIG. 9A is beingformed in a surrounding area of a part corresponding to the position ofthe via 350 or a surrounding area of a part corresponding to theposition of the chip capacitor 340 at the first conductive layer 310 orthe second conductive layer 320 in the printed circuit board in theprinted circuit board in accordance with the fifth embodiment of FIG.12A.

Similarly, the printed circuit board shown in FIG. 12A through FIG. 12Ccan function as the electromagnetic bandgap structure by penetrating thechip capacitor 340 and the filled material 380 placed in the cavityformed the board and forming the LC series connection structure by thevia 350 connected in series to the chip capacitor 340 (or the etchedpattern 370 additionally connected in series to the via 350).

Also, the printed circuit board shown in FIG. 12A can have a simplerfabrication process of the series connection structure between the chipcapacitor 340 and the via 350 than the printed circuit board shown inFIG. 6 through FIG. 10B. This will be described with reference to FIG.13A through FIG. 13F.

FIG. 13A through 13F illustrate the method for embedding a chipcapacitor in the case of the printed circuit board shown in FIG. 12A.

Referring to FIG. 13A, the printed circuit board including the firstconductive layer 310 and the first conductive layer 330 stacked in anupper part is illustrated.

Referring to FIG. 13B, the dielectric layer 330 can be removed so as toallow the cavity 380 a to be placed at a particular point of thedielectric layer 330 stacked in on the first conductive layer 310.

The formation operations of cavity 380 a through the process are forseating the chip capacitor 340 in the cavity 380 (refer to FIG. 13C) andfor electrically connecting the first electrode 341 of the chipcapacitor 340 and the first conductive layer 310. Accordingly, the size,area size and height of the cavity 380 a formed through the process canbe determined considering the size, area size and height of the chipcapacitor 340 to be embedded, and the dielectric layer 330 can beremoved to expose the first electrode 310 through the formationoperations of the cavity 380 a.

Referring to FIG. 13D, the filled material 380 can be filled in a spaceexcluding the space occupied by the chip capacitor 340 in the cavity 380a. At this time, the filled material 380 can employ an insulationmaterial to connect the first conductive layer 310 to be electricallydisconnected to the second conductive layer 320 or the first electrode341 to be electrically disconnected to the second electrode 342.

Referring to FIG. 13E, the via 350 penetrating the filled material 380and being connected to the second electrode 342 of the chip capacitor340 can formed. For example, the via 350 can be formed through adrilling process using a laser drill.

Referring to FIG. 13F, a conductive material can be stacked in so as toallow the second electrode 242 of the chip capacitor 340 to beelectrically connected to the second conductive layer 320 through thevia 350. The stacking process of the conductive material can beperformed in various ways.

For example, if the stacking process by the same conductive material isperformed, the conductive material can be charged or applied to aninside of the via 350 together with the formation of the secondconductive layer 320. Also, after firstly charging or applying theconductive material (e.g. a conductive paste, the same material as thesecond conductive layer 320 to be formed later, and the filled material)to the inside of the via 350, the conductive material (e.g. copper) toform the second conductive layer 320 can be stacked on the surfaces ofthe via 350, the dielectric layer 330 and the filled material 380. Atthis time, the via 350 can be filled with the conductive material in theinside or the conductive material can be applied to inner wallsexcluding a center area. Here, if the via 350 has the empty center area,an additional dielectric material or air can be filled in the emptycenter area.

Although the above description is related to the method of embedding thechip capacitor 340 in the printed circuit board shown in FIG. 12A, inthe case of the printed circuit board shown in FIG. 12B or FIG. 12C, theformation process of the etched pattern 370 can be added. For example,in the case of FIG. 12B, the step of forming the etched pattern 370having an open curved shape of spiral type in a surrounding areacorresponding to the position to be formed with the cavity 380 a in thefirst conductive layer 380 can be added. Also, in the case of FIG. 12C,the step of forming the etched pattern 370 in a surrounding area of apart corresponding to the position to be formed with the via 350 in thesecond conductive 320 will be able to be added.

FIG. 12A illustrates a simulation model for checking whether the seriesconnection structure between a via and a chip capacitor embedded in aprinted circuit board can be used as an electromagnetic bandgap inaccordance with the present invention, and FIG. 14B shows acomputer-simulation result when the simulation model shown in FIG. 14Ais applied.

The simulation model of FIG. 14A shows the one-band structure in whichthe printed circuit board 400 includes a noise point 501 and ameasurement point 502, and the series connection structure between thechip capacitor 340 and the via 350 is arranged between the noise point501 and the measurement point 502. The graph of FIG. 14B is the computersimulation result showing how much noise supplied to the noise point 501does reach the measurement point 502.

Referring to FIG. 14B, in the case of the simulation model of FIG. 14A,it can be recognized that the bandgap frequency has an appropriately1.5˜3.8 GHz band on a basis of a (−) 50 db shield rate. Though thissimulation result, it can be recognized again that the printed circuitboard having the series connection structure between the chip capacitor340 and the via 350, embedded in the printed circuit board, inaccordance to the present invention can function as a band reject filterby the structural property.

Although the simulation result of FIG. 14B shows the bandgap frequencyhas the appropriately 1.5˜3.8 GHz band, the bandgap frequency can bechanged according to the diameter, length, and shape of the via 350, thechange of an inductance value depending on the shape, length, area sizeand width of the etched pattern 370, the thickness and area size of thedielectric member 343 of the chip capacitor and the type and dielectricconstant of the dielectric material forming the dielectric member 343.

Accordingly, the present invention can prevent the electromagnetic wavehaving the desired frequency band by using the series connectionstructure between the chip capacitor and the via 350 embedded in theprinted circuit board as the electromagnetic bandgap structure. Also,the present invention can have simpler structure than the conventionalart (e.g. the mushroom by the metal plate and the via). This can resultin no design limitation and the difficulty of the configuration and theoutstanding property in the aspect of signal integrity.

Hitherto, although some embodiments of the present invention have beenshown and described for the above-described objects, it will beappreciated by any person of ordinary skill in the art that a largenumber of modifications, permutations and additions are possible withinthe principles and spirit of the invention, the scope of which shall bedefined by the appended claims and their equivalents.

1. A method of embedding a chip capacitor in a printed circuit boardincluding a first conductive layer and a dielectric layer placed on thefirst conductive layer, the method comprising: removing the dielectriclayer to form a cavity exposing the first conductive layer; seating achip capacitor in the cavity; filling a filled material at a spaceexcluding a space occupied by the chip capacitor in the cavity; forminga via penetrating the filled material and being connected to the chipcapacitor; and stacking a conductive material to constitute a secondconductive layer in surfaces of the via and the dielectric layer and inan surface of the filled material filled in the cavity.
 2. The method ofclaim 1, wherein the chip capacitor comprises a first electrode, adielectric member, placed on the first electrode, and a secondelectrode, placed on the dielectric member, and the first electrode isconnected to the first conductive layer, and the second electrode isconnected to the second conductive layer through the via.
 3. The methodof claim 1, further comprising: forming an etched pattern in anopen-curved line shape in a surrounding area of a part corresponding toa position in which the cavity is supposed to be formed in the firstconductive layer.
 4. The method of claim 1, wherein the etched patternhas a spiral shape.
 5. The method of claim 1, further comprising:forming an etched pattern in an open-curved line shape in a surroundingarea of a part corresponding to a position in which the via is formed inthe second conductive layer.
 6. The method of claim 1, wherein theetched pattern has a spiral shape.